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A New network multiplier using modified high order encoder and optimized hybrid adder in CMOS technology |
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PP: 159-164 |
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Author(s) |
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Pooya Asadi,
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Abstract |
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In this paper, a new low power, high speed network multiplier is presented. For increasing performance of multiplier, a
novel modified high-order encoder is proposed. Previous encoders have complicated hardware and their ability to decrease number of
input operands is low. Presented encoder uses high-order algorithm and therefore reduces number of partial products efficiently. A new
hybrid adder is presented which uses ideas of carry lookahead adder and ripple carry adder to modify final adder architecture. Previous
carry lookahead adders have large carry network and their ability to decrease noise margin is low. It uses a DCVS carry network,
which provides high speed and less wiring problems in compare with previous algorithms. Proposed hybrid adder has major effect
on multiplier efficiency. A new network array is presented which uses high performance modules. Using a new algorithm, this study
reduces critical path of tree multiplier. A novel counter is implemented which uses less transistor count and less power consumption
in compare with previous algorithms. This counter uses pass transistor technology. Transistor connections, in mentioned counter are
implemented in a new efficient way. The new multiplier has better efficiency in different electronic and algorithmic parameters in
compare with previous implementations. |
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