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A Fast-Locking Digital Delay-Locked Loop with Multiphase Outputs using Mixed-Mode-Controlled Delay Line |
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PP: 171-178 |
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Author(s) |
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Yu-Lung Lo,
Pei-Yuan Chou,
Wei-Jen Chen,
Shu-Fen Tsai,
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Abstract |
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| This paper proposes a fast-locking digital delay-locked loop (DLL) with multiphase outputs using mixed-mode-controlled
delay line (MCDL). The proposed DLL uses a dual-loop technique to control various MOS capacitors and an MOS resistor in the
MCDL to improve locking time and reduce static phase error. The chip was fabricated using a 0.35 mm standard CMOS process with
a 3.3 V supply voltage. The measurement results showed that the proposed DLL can operate correctly with the input clock frequency
varying from 145 MHz to 245 MHz. After the DLL is locked, it can generate four-phase clocks within a single clock cycle. At 180
MHz, the measured root-mean-square jitter and peak-to-peak jitter were 10 ps and 70 ps, respectively. The total power consumption of
the DLL was 15 mW, and the active area of the DLL was 0.086 mm2. The locking time was less than 30 clock cycles. |
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