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D Flip Flop with Different Technologies |
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PP: 1-6 |
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Author(s) |
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Amit Grover,
Sumer Singh,
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Abstract |
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| This article explains a new implementation of efficient D-Flip-Flop (DFF) using Gate-Diffusion-Input (GDI) technique,
PowerPC, DSTC, and HLFF. This DFF design allows reducing power-delay product and area of the circuit, while maintaining low
complexity of logic design. Performance comparison with other DFF design techniques is presented, with respect to gate area, number of
devices, delay and power dissipation, showing advantages and drawbacks of GDI DFF as compared to other methods. The performance
is carried out by HSPICE simulation with 180 nm & 90 nm CMOS technology. |
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