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3D-DCT Chip Design for 3D Multi-view Video Compression |
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PP: 567S-572S |
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Author(s) |
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Yu-Cheng Fan,
Shan-Ann Chen,
Kuo-Gi Wu,
Jun-Lin You,
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Abstract |
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| This paper describes the implementation of three dimensional (3D) data decreasing strategy. Due to the upcoming of 3D generation, the abundant data accompany with multi-view video. Therefore, video compression has become the most important process of dealing with 3D data. The purpose of this paper is to use 3D discrete cosine transform (DCT) to transfer data into frequency domain. In addition, it has the characters of gathering energy together in order to achieve the goal of data compression. First, we transform nine different views into grey to make data become easily to calculate. Second, we propose a disparity estimation algorithm to calculate the different views and block matching full search algorithm (BMFS) to find out the minimum of SAD. That is to say, this is the most similar block. According to the displacements of two images, we can find out its motion vector, and then use motion vector to compensate the present image. Third, we subtract compensated image from the original one and get the image difference of two images. By doing so, the similar part will be deleted, and it will also decrease the resource cost. Fourth, we transform the difference with 3D-DCT. Owing to 3D-DCT, which has the character of gathering energy; hence, all energy will be gathered in one corner. Finally, we quantize to the data, which had already been transformed, and delete the redundant part to achieve the effect of data compression. The result lead to the conclusion that 3D-DCT chip produces efficient results. The scheme speeds up 47% of the chip. Besides, the presented method decreases 14.4% logic gate count of this chip. Therefore, the power consumption decrease 16% at the same time. We adopt TSMC 0.18 um process to achieve the chip and perform 3D-DCT chip design for 3D multi-view video compression. |
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