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Analysis and Design of Power Optimized Pipelined Processor Using Micrologic Elements |
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PP: 107-114 |
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doi:10.18576/amis/13S110
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Author(s) |
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C. Aarthi,
R. K. Gnanamurthy,
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Abstract |
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| A delay buffer consists of gated clocks, a driver tree, and a memory unit in the pipelined processor that uses several novel techniques and methodologies to reduce its power consumption. In this paper a new circuit design and analysis of a low-power delay buffer using micrologics (MLEs) is proposed. Delay buffers of different lengths are needed in the pipelined CPU and FFT architecture. Several implementations of DET flip-flops, clock gating C elements, shift registers, and buffers are compared with micrologic elements such as F element, H element, S element and B element. These micrologic elements produce very low propagation delays which enhance its use in high-speed systems. A new simulation and optimization approach is presented, targeting the power consumption. The different comparison analysis reveals the sources of performance and power consumption bottlenecks in different design styles. The implementation is carried out in standard cells of 0.18 μm CMOS technology. Both simulation and experimental results show great improvement in power consumption.
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