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DynaPack: A Dynamic Scheduling Hardware Mechanism for a VLIW Processor |
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PP: 983-991 |
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Author(s) |
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Slo-Li Chu,
Geng-Siao Li,
Ren-Quan Liu,
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Abstract |
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| Continuously growing of semiconductor technology makes the processor architectures more complicated to improve the instruction level parallelism. In the mechanisms of improving instruction level parallelism, VLIW is an attractive technique to improve parallelism without complicated instruction reordering mechanism for dynamic execution. The instruction scheduling is relied on VLIW compiler to select and pack suitable instructions into a VLIW bundle. The programs have to be recompiled accordingly. This drawback limits the popularity of VLIW processors. In this paper, a novel VLIW processor, Avatar, is proposed to overcome the above incompatible problems. By integration with a novel scheduling/packing mechanism, DynaPack, this processor can directly execute the legacy MIPS32 binary codes without recompilation, and fulfill the instruction level parallelism of Avatar VLIW processor. By integrating a new instruction scheduling/packing hardware mechanism, DynaPack can analyze the dependence relations of instructions, maintain their correctness, and pack suitable instructions into a VLIW bundle on-the-fly. The experimental result reveals that Avatar processor with DynaPack mechanism can obtain up to 3.4 instructions per cycle. The chip fabrication results of DynaPack mechanism can achieve 111 MHz by consuming 19343886µm2
under TSMC 0.13µm technology library
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